The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a fin transistor.
As semiconductor devices become highly integrated, conventional two-dimensional transistor structures have some limitations. In particular, for high-speed devices, two-dimensional transistor structures often do not satisfy the required current drive.
Fin field effect transistors (FETs) and saddle-type fin FETs are two examples that attempt to overcome the aforementioned limitation. These fin FETS and saddle-type fin FETs usually uses three surfaces as channels, and thus, they provide good current drive, and improve back bias dependency.
FIGS. 1A to 1D are cross-sectional views illustrating a method for fabricating a fin transistor. FIG. 2 illustrates a top view of the fin transistor fabricated by the method described in FIGS. 1A to 1D. In FIGS. 1A to 1D and FIG. 2, cut plane X-X′ is directed along a major axis of an active region 15A, while cut plane Y-Y′ is directed along a region where gate electrodes 19 are to be formed.
Referring to FIG. 1A, a pad oxide layer 12 and a pad nitride layer 13 are formed on a substrate 11, and etched using an isolation mask (not shown). The substrate 11 is etched to a certain depth using the pad nitride layer 13 as an etch barrier to form trenches 14. Referring to FIG. 1B, an oxide layer is deposited until the trenches 14 are filled. The wafer is then subjected to a chemical mechanical polishing (CMP) to form field oxide layers 15. The field oxide layers 15 are used for isolation and define an active region 15A. Referring to FIG. 1C, a line type fin mask 16 is formed over certain regions of the resultant structure illustrated in FIG. 1C. The field oxide layers 15 are recessed to a certain depth using the fin mask 16 as an etch barrier to form fins 17B. Reference numeral 17A denotes recesses obtained after the field oxide layers 15 are recessed. Referring to FIG. 1D, the fin mask 16 is removed, and a gate oxide layer 18 and a gate electrode layer (not shown) are formed and patterned to form gate electrodes 19.
When the fins 17B are formed, the top portions of the fins 17B are often damaged. Particularly, when the field oxide layers 15 are etched, the top portions of the fins 17B are often etched away. As illustrated in FIG. 1C, the loss may occur in the top and lateral directions T and L.
FIG. 3A illustrates an image of a fin with a damaged top portion. Due to the loss of the top portion of the fin, a tapered top is generated. As mentioned, the loss of the top portion of the fin is generally incurred when the field oxide layer is etched using an oxide etching gas. Particularly, the loss of the top portion of the fin is usually incurred when the pad nitride layer 13 does not sufficiently function as an etch barrier because of the oxide etching gas.
A fin is in a region where the channel is to be formed and generally determines the shape of the transistor. If a fin has a small critical dimension (CD), the loss of the top portion of the fin often leads to a decrease in the CD of the fin. Thus, if the fin is likely to be sharply tapered, it may make it difficult to achieve the desired CD reproducibility of a channel.
As similar to the aforementioned loss of the top portion of the fin, when a saddle-type fin pattern for a saddle-type fin FET is formed, the top portion of the fin pattern is likely to be damaged. Also, as the recessed depth of the field oxide layer to form a fin or a saddle-type fin pattern increases, the loss of the top portion of the fin or the saddle-type fin pattern tends to increase. FIG. 3B illustrates an image of a damaged saddle-type fin. Due to the severe damage (loss), the saddle-type fin pattern often exhibits a tapered top portion.